The second generation current conveyor (CCII) is becoming a popular design choice for analog very large-scale integration (VLSI) designs. This paper uses it for analog implementation of some piecewise linear neural models dubbed two point, three point, and four point piecewise linear (2PWL, 3PWL, and 4PWL, respectively) approximations of the Izhikevich spiking neuron model [1]. The proposed design is also reconfigurable as the parameters can be tuned during operations. The design has been established to be flexible against a small range of process conditions using threshold voltage and oxide thickness variations. Thus, it can potentially be applicable for the development of VLSI neuromorphic analog chips. The current work is an extension of Sharifipoor and Ahmadi’s earlier work [2] where 2PWL was introduced. Apart from the introduction of 3PWL and 4PWL models, the current paper also includes a detailed bifurcation analysis.

There are, nevertheless, a number of issues that need to be addressed. The simulation does not verify its practicality for all extreme process corners, nor is it practically tested by silicon fabrication. Furthermore, the proposed circuit does not excel compared to the Izhikevich implementation (table 4), which uses merely 14 transistors and consumes a meager 9 picojoules of power. It is understood that the use of CCII is responsible for the increased number of transistors and power consumption; however, based on the specific fabrication-level results from Wijekoon and Dudek [3], the paper lacks an explanation of why the CCII approach is worthy of exploration.