The much-needed downscaling of different core system architectures is significantly challenged by static power dissipation. The authors present a solution via middleware-transparent intermittent computing, utilizing a newly developed non-volatile flip-flop design, NV clustering, which is a standardized methodology for synthesizing optimized non-volatile architectures. It utilizes a logic-embedded flip-flop (LE-FF) “developed to realize rudimentary Boolean logic functions along with an inherent state-holding capability within a compact footprint,” resulting in area, complexity, and power reduction. NV clustering instantiates “the LE-FF library cells within conventional register transfer language (RTL) specifications,” thus “cluster[ing] together logic and NV state-holding functionality.”

The paper introduces “non-volatile elements including non-volatile memories (NVMs) and non-volatile flip-flops (NV-FFs),” and their role as non-volatile datapaths in designing a normally-off computing architecture. Moreover, it achieves “power failure resilient processing” while maintaining the advantageous area and performance of intermittent processors.

The results elaborate on, and thoroughly analyze, NV clustering performance characteristics (including power, delay, and area), while honestly expounding on write operation overhead for non-volatile elements compared with MOS-based architectures (which are justified in intermittent computing applications). The authors prove the superiority of their optimized LE-FF NV clustering model in a wide range of large-scale benchmarks, maintaining better area reduction and power delay over NV-FF at the 45 nanometer (nm) technology scale.

The introduced NV clustering model will significantly contribute to the performance enhancement of system architectures that cope with the special power, space, and delay needs of future applications.